1. Field of the Invention
The present invention relates to a semiconductor device, particularly to a high-withstand-voltage npn transistor used to drive an ABS (Antilock Brake System), an air bag, and a display of an automobile, drive a fluorescent display panel, and control a motor.
2. Description of the Background Art
FIG. 16 is a sectional view of a conventional npn transistor. An n+-type buried layer 102 is located on a pxe2x88x92-type substrate 101 and an nxe2x88x92-type epitaxial layer 104 is formed so as to cover the n+-type buried layer 102 and the pxe2x88x92-type substrate 101. The substrate denotes a semiconductor substrate in the present invention. A p+-type diffused layer 116 formed so as to reach the pxe2x88x92-type substrate 101 by diffusion from the surface of the nxe2x88x92-type epitaxial layer 104 functions for element separation and moreover, a LOCOS oxide film 106 is formed on the surface of the layer 116. Moreover, the following are formed on the layer 116: an oxide film formed by thermally oxidizing the surface of the nxe2x88x92-type epitaxial layer. 104 up to a thickness of tens of nanometers to adjust an injection depth (not illustrated), a p+-type diffused layer 118 formed by injection from the surface of the oxide film, and an n+-type diffused layer 109 formed by injection from the surface of the p+-type diffused layer 118. Moreover, a p+-type diffused layer 110 formed by injection from the surface of the p+-type diffused layer 116 is formed as a base contact and a oxide film layer 111 is formed on outermost surfaces of the LOCOS oxide film 106, n+-type diffused layer 109, and p+-type diffused layer 110 so as to cover them. Furthermore, a wiring 112a, 112b, 112c formed in a contact hole formed to be reached to the n+-type diffused layer 109 and p+-type diffused layer 110 from the surface of the oxide-film layer 111 by dry etching so as to bury the contact hole.
Then, a method for fabricating the structure shown in FIG. 16 is described below by referring to FIGS. 17 and 18. First, the surface of the pxe2x88x92-type substrate 101 is oxidized and photoengraving is performed to remove an oxide film. Then, the n+-type buried layer 102 is formed by injecting antimony into the pxe2x88x92-type substrate 101, and heating the substrate 101 to 1,240xc2x0 C. and thereby driving it to remove the oxide film from the surface of the pxe2x88x92-type substrate 101. Then, as shown in FIG. 17, the nxe2x88x92-type epitaxial layer 104 is formed on the outermost surface of the pxe2x88x92-type substrate 101 on which the n+-type buried layer 102 is formed.
Then, the surface of the nxe2x88x92-type epitaxial layer 104 is oxidized up to hundreds of nanometers to perform photoengraving, inject boron, and perform driving at 1,180xc2x0 C., and form the p+-type diffused layer 116 used for element separation (refer to FIGS. 17 and 18). Then, oxide films are removed from outermost surfaces of the p+-type diffused layer 116 and nxe2x88x92-type epitaxial layer 104 to form an oxide film having a thickness of tens of nanometers. Then, a nitride film is deposited to perform photoengraving and then, the nitride film is removed to form a LOCOS oxide film. Then, the oxide film at a thickness of tens of nanometers and the LOCOS oxide film 106 are removed up to a thickness of tens of nanometers to form an oxide film 117 up to a thickness of 10 to 50 nm. Then, resist is applied to perform patterning and boron is injected to perform driving and form a p+-type diffused layer 118 serving as the base region of npn transistor. Next, photoengraving is performed in order to form a n+-type diffused layer 109 serving as the emitter region of the npn transistor, and arsenide is injected and driving is performed at 900xc2x0 C. in a nitride atmosphere. Then, as shown in FIG. 18, to improve the ohmic contact of the base contact of the npn transistor, the p+-type diffused layer 110 is formed by injecting BF2.
Then, the oxide-film layer 111 is deposited and photoengraving is performed to form a contact hole on the oxide-film layer 111 so as to contact each diffused-layer region and photoengraving is performed by sputtering aluminum. Then, as shown in FIG. 16, aluminum is removed to form an aluminum electrode contacting each diffused-layer region.
By using the above structure, it is possible to obtain an npn transistor having a high withstand voltage and a high operation speed.
In the case of the npn transistor having the above configuration, however, the base region is common to the substrate. Therefore, when driving a transistor for emitter grounding, it is necessary to apply to an emitter a potential lower than that of the base region whose potential is common to a substrate having a zero potential. Therefore, it is necessary to constitute a negative-voltage source in an IC (Integrated Circuit). Thus, a circuit becomes complex, the number of fabrication steps increases, and the cost increases. Therefore, it has been desired to develop an npn transistor in which a potential can be more easily set to each terminal.
It is a main object of the present invention to provide an npn transistor in which it is unnecessary to constitute a negative-voltage source in an IC for emitter grounding and it is possible to easily set the potential of each terminal. It is another object of the present invention to provide an npn transistor achieving the above main object and moreover, superior in characteristics such as a withstand-voltage performance and a current amplification factor.
A semiconductor device of the present invention is provided with an n-type buried layer formed on a p-type semiconductor substrate, a p-type buried layer formed on the n-type buried layer, an n-type epitaxial layer formed on a p-type semiconductor substrate, the n-type buried layer, and the p-type buried layer so as to cover them, an n-type emitter region, a p-type base region encircling the n-type emitter region by contacting it from the inside, and a n-type collector region which are respectively located at the surface of the n-type epitaxial layer, and a p-type outer-periphery layer located at the surface of the n-type epitaxial layer, encircling the n-type emitter region, the p-type base region, and the n-type collector region from the circumference when viewed from above. Moreover, in the case of this semiconductor device, the n-type epitaxial layer includes an n-type encirclement layer contacting the outer periphery of the p-type outer-periphery layer and the p-type base region and p-type buried layer as well as the p-type outer-periphery layer and p-type buried layer are respectively continued to divide the n-type epitaxial layer and separate the n-type collector region from the p-type semiconductor substrate, and the n-type buried layer and the n-type encirclement layer are continued to separate the continued p-type buried layer, p-type base region, and p-type outer-periphery layer from the p-type semiconductor substrate.
According to the above configuration, terminal regions of the emitter, base, and collector regions are separated from the p-type substrate. That is, it is possible to lift the npn transistor from the p-type substrate. Therefore, it is possible to arbitrarily set the potential of each terminal to zero potential or higher correspondingly to a wiring pattern. For example, when using a wiring pattern for emitter grounding, it is possible to apply an arbitrary positive potential to a base or collector terminal by connecting an emitter terminal to the p-type substrate to make the potential common to that of the substrate. Therefore, it is unnecessary to set a negative-voltage source required to drive the emitter of a conventional npn transistor in which a base region is electrically connected with a substrate in an IC in emitter grounding. That is, the above emitter potential is accidentally made common to the substrate potential because it is convenient for wiring to use the substrate potential in setting zero potential. Originally, it is possible to set a potential to the above three terminals independently of a substrate potential. Therefore, it is possible to equalize the potential of a terminal to be grounded with that of the substrate for convenience"" sake of wiring in accordance with the wiring pattern of the terminal and set the potential of other terminal to an arbitrary positive potential. In this case, the npn transistor easily obtains a high withstand voltage because of the reason to be described later in the generally-used emitter grounding.
Moreover, because the collector region is separated from the p-type semiconductor substrate by the p-type buried layer, p-type base region, and p-type outer-periphery layer, it is possible to greatly suppress a leak current compared to the case of a conventional structure in which a collector region contacts a semiconductor substrate.
In the case of the above semiconductor device of the present invention, it is possible to equalize the potential of the p-type outer-periphery layer with that of the n-type encirclement layer by wiring connection.
According to the above configuration, a backward bias voltage is applied to pn junctions between the p-type semiconductor substrate, n-type buried layer, and n-type encirclement layer in the generally-used emitter grounding. Therefore, a depletion layer is formed at each pn junction and the depletion layer bears the voltage. Therefore, it is possible to improve the withstand-voltage performance.
In the case of the above semiconductor device of the present invention, it is preferable that the p-type-impurity concentration of the p-type semiconductor substrate is lower than n-type-impurity concentrations of the n-type buried layer and n-type epitaxial layer.
When a backward bias voltage is applied to pn junctions between the p-type semiconductor substrate, n-type buried layer, and n-type encirclement layer, the depletion-layer width is extended to a lower impurity-concentration side so as to be inversely proportional to the concentration ratio. By making the p-type-impurity concentration of the p-type semiconductor substrate lower than the n-type-impurity concentration of the opposite side of a junction portion, a depletion layer with a larger width extends toward the p-type semiconductor substrate. Thereby, because the width of the depletion layer can be further increased, it is possible to bear a higher voltage and further improve the withstand-voltage performance.
In the case of the above semiconductor device of the present invention, it is preferable that the p-type base region, n-type emitter region, and n-type collector region are annularly arranged when viewed from above by sharing the central portion.
For example, in the case of a quadrangular npn transistor when viewed from above, because electric fields are concentrated on corners, the withstand-voltage performance is deteriorated. By annularly arranging the terminal regions as described above, it is possible to prevent concentration of electric fields and as a result, improve the withstand-voltage performance.
For the above semiconductor device of the present invention, it is possible to use a configuration in which the p-type base region includes a p-type-base-contact-side base region contacting the base contact and a p-type-buried-layer-side base region contacting the p-type buried layer and containing p-type impurities at a concentration lower than that of the base-contact-side base region.
According to the above configuration, it is possible to further improve the ohmic contact in the connection from the base terminal up to the base region via the base contact. Moreover, it is possible to prevent a depletion layer produced at a pn junction formed between the base region contacting the n-type epitaxial layer and the n-type epitaxial layer from easily grown in the high-concentration base-contact-side base region around the emitter region by forming the depletion layer with a large width in the buried-layer-side base region having a low impurity concentration. Therefore, it is possible to bear a voltage by the depletion layer and improve the withstand voltage between the emitter and collector because the depletion layer does not easily reach the emitter. In the case of the present invention, a region to which a base terminal is connected is referred to as a base contact that is used separately from the base region encircling the emitter region. Other regions to which an emitter terminal and a collector terminal are connected are referred to as an emitter region and a collector region.
In the case of the above semiconductor device of the present invention, it is preferable that the p-type-impurity concentration in the effective base width serving as a region between the n-type emitter region in the p-type base region contacting the n-type epitaxial layer and the n-type epitaxial layer is higher than the n-type-impurity concentration of the n-type epitaxial layer encircling the n-type collector region formed on the surface of the n-type epitaxial layer by contacting the layer from the inside.
Improvement of the withstand voltage of a pnp transistor denotes improvement of the withstand voltage between an emitter and a collector. Improvement of the withstand voltage between the emitter and collector is realized by improving the withstand voltage between the base and collector. In the case of an npn transistor, it is possible to apply a backward bias voltage to a pn junction serving as a base-collector interface by applying a positive potential to be easily used when mounted to a general system to the collector and thereby, a depletion layer is formed and a voltage can be borne by the depletion layer. Therefore, an npn transistor easily outputs a withstand voltage compared to a pnp transistor.
Moreover, the withstand voltage between an emitter and a collector is a voltage until the depletion layer formed at the above pn junction reaches an emitter region when raising the above backward bias voltage. By using the above impurity-concentration configuration, a depletion layer formed at a pn junction expands by increasing its width inversely proportionally to an impurity concentration. Therefore, the depletion layer more greatly expands on an n-type epitaxial layer than in a p-type base region. Therefore, a depletion layer formed at a pn junction does not easily reach an emitter region. Therefore, the above impurity-concentration configuration makes it possible to further improve the withstand-voltage performance of an npn transistor.
In the case of the above semiconductor device of the present invention, it is preferable that the effective base width serving as a region from a pn junction formed by an n-type epitaxial layer encircling an n-type collector region formed on the surface of an n-type epitaxial layer by contacting the region from the inside and a p-type base region contacting the n-type epitaxial layer up to an emitter region is larger than the distance from the pn junction up to the collector region.
According to the above impurity-concentration configuration, the depletion layer formed at the pn junction does not easily reach the emitter region by increasing the distance from the position of the pn junction up to the emitter region in addition to the fact of preventing the depletion layer from easily reaching the emitter region. The above configuration makes it possible to improve the withstand-voltage performance by making the distance in the p-type base region from the position of the pn junction up to the emitter region larger than the distance in the n-type epitaxial layer from the position of the pn junction up to the collector region.
For the above semiconductor device of the present invention, it is possible to use a configuration in which a gate electrode is formed on the effective base width serving as a range from an n-type emitter region up to an n-type epitaxial layer encircling an n-type collector region in a p-type base region through an insulating film.
By applying a positive voltage equal to the potential of a base electrode to the above gate electrode, it is possible to form an n-type inversion layer on the surface of a p-type base region forming an effective base width. Therefore, an n-type channel extending from the emitter region up to the collector region is formed, collector current can be increased, and thereby, a current amplification factor hFE can be increased.
The above semiconductor device of the present invention can be provided with an n-type enlarged emitter region containing n-type impurities whose concentration is lower than that of an n-type emitter region, encircling an n-type emitter region by contacting it from the inside, and being formed by dividing a p-type base region so as to reach up to a p-type buried layer.
According to the above configuration, when an abnormal positive voltage is applied to the emitter, a depletion layer formed at the pn junction on the emitter-base interface further increases its width in an n-type enlarged emitter region at a position far from the emitter region. This is because the impurity concentration of the n-type enlarged emitter region is lowered. Therefore, because the depletion layer bears the voltage, it is possible to improve the withstand voltage between the emitter and base. As a result, it is possible to omit a large diode or high resistance for protecting the emitter.
In the case of the above semiconductor device of the present invention, it is preferable that the p-type-impurity concentration on the surface of the effective base width is equal to or lower than the p-type-impurity concentration of the buried-layer-side base region.
According to the above configuration, it is possible to lower the impurity concentration of a portion where a channel is formed without adding another step, secure a high current amplification factor, and improve the withstand voltage between the base and collector.
In the case of the above semiconductor device of the present invention, it is preferable that the insulating film formed between the region of the effective base width and the gate electrode has a thickness of 200 nm or more (claim 11).
Because the gate electrode and the base terminal are set to the same potential, it is possible to improve the withstand voltage between the base and collector by increasing the thickness of the gate insulating film and securing the high current amplification factor hFE.